1. Field of the Invention
This invention relates to a semiconductor device and to a method for its preparation. More particularly, this invention relates to a semiconductor device with improved breakdown voltage and integration density, and to a method for its preparation.
2. Description of the Prior Art
Generally, in a bipolar semiconductor device, isolation is necessary to separate electrically between elements, and various techniques for this purpose have been offered.
As one example of such techniques, V-groove isolation with polycrystalline silicon (VIP) is a well known method. This method utilizes a V-shaped groove as an isolation region between elements in the bipolar semiconductor device. The VIP method is explained in detail in the following description and is very important with respect to the present invention. To illustrate the prior art semiconductor device and method for manufacturing the same, reference is made to FIGS. 1-12.
FIG. 1 shows a partial cross-section of a P type silicon semiconductor substrate 10. In FIG. 1, after forming an oxide film 12 over the entire surface of the P type silicon semiconductor substrate 10 and selectively forming windows 14, 16 by patterning the oxide film 12, impurities are diffused through the windows 14, 16; and thereby the N+ type buried layers 18, 20 are formed in the surface of the semiconductor substrate 10.
Referring to FIG. 2, after removing the oxide film 12, an N- type silicon semiconductor layer 22 is formed over the entire area of the buried layers 18, 20 and the semiconductor substrate 10 by epitaxial growth. Here, the Miller indices of the semiconductor substrate 10 are (100), the depth of the buried layers 18, 20 is about 3 to 5 microns and the thickness of the epitaxial layer 22 is about 2 to 3 microns.
Referring to FIG. 3, an oxide film 24 and a silicon niride film 26 are formed on the epitaxial layer 22 by oxidation and SiN deposition, respectively. Then the silicon nitride film 26 and the oxide film 24 are subject to patterning and thereby the windows 28, 30, 32 are formed.
Referring to FIG. 4, V-shape etching is performed in the epitaxial layer 22 and the semiconductor substrate 10 by using the patterned silicon nitride film 24 as a mask, thereby V-shaped grooves (isolation regions) 29, 31, 33 can be formed. Here, as an etching solution, an anisotropic etching solution such as potassium hydroxide (KOH) solution with isopropyl alcohol or ethylene diamine with pyrocatechol is used.
Referring to FIG. 5, oxide films 34, 36, 38 are formed in the V-shape grooves 29, 31, 33 by oxidation.
Referring to FIG. 6, the polycrystalline silicon film 40 is formed on the entire surface of the device by chemical vapor deposition (CVD). The thickness of the polycrystalline silicon film 40 should be at least such that the V-shape grooves 29, 31, 33 are sufficiently buried.
Referring to FIG. 7, the surface of the device is polished so that the polycrystalline silicon films 40 remain only within the V-shape grooves 29, 31, 33.
Referring to FIG. 8, oxide films 42, 44, 46 are formed in the surface of the remaining polycrystalline silicon films 40 by oxidation. Thereby, the polycrystalline silicon films 40 are totally buried within the oxide films.
Referring to FIG. 9, the silicon nitride film 26 is removed by etching, for instance, using phosphoric acid (H.sub.3 PO.sub.4). In FIG. 9, the oxide film is represented by the numeral 24.
Referring to FIG. 10, P type base regions 48, 50 are formed by ion implantation using, for example, a photoresist as a mask. Here, it should be understood that a diffusion method may also be employed to form the P type base regions 48, 50 as is well known in the prior art.
Referring to FIG. 11, collector electrode windows 52, 62 and emitter electrode windows 56, 58 are formed by patterning the oxide film 24. Then, impurities are diffused through these windows, whereby N+ type collector contact regions 64, 70 and N+ type emitter regions 66, 68 are formed. Thereafter, base electrode windows 54, 60 are formed by patterning the oxide film 24.
Referring to FIG. 12, an aluminum electrode material 72 is evaporated on the entire surface of the device. Then, the aluminum 72 is selectively removed to define a conductor wiring area. Phosphoric acid with an additive of nitric acid may be used for etching the aluminum.
In a semiconductor device as mentioned above, the semiconductor layer 22 formed by the epitaxial growth was relatively thick. However, more recently, such epitaxial layer 22 must be thin because the width of the isolation regions 29, 31, 33 is narrowed so as to obtain high integration density. Usually, the depth of the V-shape groove is determined as about 0.7.times. width of the isolation region.
As can be seen in FIG. 10, a PNP configuration is formed by the P type base region 48 (50), the N- type epitaxial layer 22 and the P type semiconductor substrate 10. Therefore, when the epitaxial layer 22 becomes thin, the base region 48 (50) and the semiconductor substrate 10 are likely to suffer punch through.
As a method for avoiding such punch through, the N type impurity concentration of the epitaxial layer 22 can be increased. However, in this case, the depletion layer between the base and the collector becomes narrow, and accordingly the capacitance between the base and the collector increases. Therefore, it is not desirable to increase the N type impurity concentration of the epitaxial layer 22 when a high speed transistor is desired.
FIG. 13 shows another example of the prior art bipolar semiconductor device. In FIG. 13, the configuration of the isoplanar type bipolar semiconductor device which has an isolation region 76 comprising, for example, silicon dioxide is disclosed. In FIG. 13, the same reference numerals as that of FIGS. 1 to 13 indicate the same portions.
In this example, the generation of punch through between the base region 48 (50) and the semiconductor substrate 10 is prevented since the N+ type buried layer 18 (20) makes contact with the isolation region. In order to employ such configuration, the isolation region 76 must be wide and, therefore, it is difficult to obtain high integration density. Of course, it is impossible to employ such method, i.e., making the N+ buried layer contact with the isolation region, in the case of the above mentioned VIP method. This prior art method is therefore not useful to isolate between elements.